1) Field
Embodiments of the invention are in the field of semiconductor devices and, in particular, methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer.
2) Description of Related Art
For the past several decades, the scaling of features in integrated circuits has been the driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of logic and memory devices on a microprocessor, lending to the fabrication of products with increased complexity. Scaling has not been without consequence, however. As the dimensions of the fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the performance requirements of the materials used in these building blocks have become exceedingly demanding. One example is the change from poly-crystalline silicon to metal gate electrodes in complimentary metal-oxide-semiconductor (CMOS) transistors, starting at around the 45 nanometer or 32 nanometer technology nodes.
Metal gate electrodes for CMOS transistors can be fabricated in a replacement gate integration scheme. However, as constraints on dimensions increase, problems may arise with conventional approaches. For example, FIGS. 1A-1C illustrate cross-sectional views representing operations in a conventional replacement gate integration scheme.
Referring to FIG. 1A, a partially completed semiconductor device 100 is formed in and above a substrate 102. Source and drain regions 104 define a channel region 106 in substrate 102 and underneath a gate dielectric layer 108. A trench 110 is formed in a dielectric layer 112 and, in particular, in between a pair of dielectric spacers 114. A gate electrode for semiconductor device 100 may ultimately be formed in trench 110.
In a replacement gate integration scheme, the gate electrode is formed by depositing a metal layer over a partially completed semiconductor device to fill at least a portion of a trench 110. Referring to FIG. 1B, a gate electrode is formed by depositing a metal layer 116 over partially completed semiconductor device 100 to fill a portion of trench 110. However, metal layer 116 may be pinched-off at the top of trench 110 prior to completion of the filling of trench 110. Hence, a void 120 may undesirably be formed within trench 110, as depicted in FIG. 1B.
Referring to FIG. 1C, metal layer 116 has been planarized to form a planarized metal layer 118, exposing void 120 formed within trench 110. Void 120 may undesirably collect residue from processing steps, such as slurry residue from a chemical-mechanical polishing step used to planarize metal layer 116. The inclusion of such residue may interfere with subsequent process steps and, if retained in a completed semiconductor device, may impact the performance or function of the completed semiconductor device.